GSOC Organizations

CHIPS Alliance

Open source IP, tools & standards for ASIC/FPGA

Technologies

fpga

chisel

risc-v

systemverilog

ASIC

Topics

soc

IP cores

ASIC design

HDL

chiplets

https://chipsalliance.org/

Mailing List / Forum

Projects

Contributor

Karim Tera

Verible SystemVerilog Preprocessor

The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser,...

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Contributor

Lucca Silva

Improving the automatic layout generation of the mixed-signal temperature sensor block in OpenFASOC

OpenFASOC is an open-source framework for autonomous generation of optimized integrated circuit blocks given user specifications. It is a growing...

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Contributor

saicharan00112

Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC

OpenFASOC, an automated SOC generator, is enabling chip enthusiasts to develop circuits/macros with a software approach. Circuits must not only be...

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